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74LVC2G125
Dual bus buffer/line driver; 3-state
Rev. 10 -- 11 June 2008 Product data sheet
1. General description
The 74LVC2G125 provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (pin nOE). A HIGH-level at pin nOE causes the output to assume a high-impedance OFF-state. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.
2. Features
I I I I Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: N JESD8-7 (1.65 V to 1.95 V) N JESD8-5 (2.3 V to 2.7 V) N JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V 24 mA output drive (VCC = 3.0 V) CMOS low-power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options Specified from -40 C to +85 C and -40 C to +125 C
I
I I I I I I I
NXP Semiconductors
74LVC2G125
Dual bus buffer/line driver; 3-state
3. Ordering information
Table 1. Ordering information Package Temperature range Name 74LVC2G125DP 74LVC2G125DC 74LVC2G125GT 74LVC2G125GD 74LVC2G125GM -40 C to +125 C -40 C to +125 C -40 C to +125 C -40 C to +125 C -40 C to +125 C TSSOP8 VSSOP8 XSON8 XSON8U XQFN8U Description plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm Version SOT505-2 Type number
plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm plastic extremely thin small outline package; no leads; SOT833-1 8 terminals; body 1 x 1.95 x 0.5 mm plastic extremely thin small outline package; no leads; SOT996-2 8 terminals; UTLP based; body 3 x 2 x 0.5 mm plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm SOT902-1
4. Marking
Table 2. Marking codes Marking code V25 V25 V25 V25 V25 Type number 74LVC2G125DP 74LVC2G125DC 74LVC2G125GT 74LVC2G125GD 74LVC2G125GM
5. Functional diagram
74LVC2G125
1A 1OE 2A 2OE EN2
mna941 001aae009
74LVC2G125
1Y EN1 2Y 2 1
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74LVC2G125_10
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 10 -- 11 June 2008
2 of 17
NXP Semiconductors
74LVC2G125
Dual bus buffer/line driver; 3-state
6. Pinning information
6.1 Pinning
74LVC2G125
1OE 1 8 VCC
1A
2
7
2OE
74LVC2G125
1OE 1A 2Y GND 1 2 3 4
001aab738
8 7 6 5
VCC 2OE 1Y 2A
2Y
3
6
1Y
GND
4
5
2A
001aab739
Transparent top view
Fig 3.
Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8)
Fig 4.
Pin configuration SOT833-1 (XSON8)
74LVC2G125
terminal 1 index area 2OE 1 VCC 8
74LVC2G125
1OE 1A 2Y GND 1 2 3 4 8 7 6 5 VCC
7
1OE
1Y 2OE 1Y 2A 2A
2
6
1A
3 4
5
2Y
GND
001aae010
001aai243
Transparent top view
Transparent top view
Fig 5.
Pin configuration XSON8
Fig 6.
Pin configuration XQFN8U
6.2 Pin description
Table 3. Symbol Pin description Pin SOT505-2, SOT765-1, SOT833-1 and SOT996-2 1OE, 2OE 1A, 2A GND 1Y, 2Y VCC
74LVC2G125_10
Description SOT902-1 7, 1 6, 3 4 2, 5 8 output enable input (active LOW) data input ground (0 V) data output supply voltage
(c) NXP B.V. 2008. All rights reserved.
1, 7 2, 5 4 6, 3 8
Product data sheet
Rev. 10 -- 11 June 2008
3 of 17
NXP Semiconductors
74LVC2G125
Dual bus buffer/line driver; 3-state
7. Functional description
Table 4. Control nOE L L H
[1]
Function table[1] Input nA L H X Output nY L H Z
H = HIGH voltage level; L = LOW voltage level; X = don't care; Z = high-impedance OFF-state.
8. Limiting values
Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground 0 V). Symbol VCC IIK VI IOK VO Parameter supply voltage input clamping current input voltage output clamping current output voltage VO > VCC or VO < 0 V Enable mode Disable mode Power-down mode IO ICC IGND Tstg Ptot
[1] [2] [3]
[1] [1] [1][2]
Conditions VI < 0 V
[1]
Min -0.5 -50 -0.5 -0.5 -0.5 -0.5 -100 -65
Max +6.5 +6.5 50 VCC + 0.5 +6.5 +6.5 50 100 +150 300
Unit V mA V mA V V V mA mA mA C mW
output current supply current ground current storage temperature total power dissipation
VO = 0 V to VCC
Tamb = -40 C to +125 C
[3]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K. For XSON8, XSON8U and XQFN8U packages: above 45 C the value of Ptot derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 6. Symbol VCC VI VO Operating conditions Parameter supply voltage input voltage output voltage VCC = 1.65 V to 5.5 V; Enable mode VCC = 1.65 V to 5.5 V; Disable mode VCC = 0 V; Power-down mode Conditions Min 1.65 0 0 0 0 Max 5.5 5.5 VCC 5.5 5.5 Unit V V V V V
74LVC2G125_10
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 10 -- 11 June 2008
4 of 17
NXP Semiconductors
74LVC2G125
Dual bus buffer/line driver; 3-state
Table 6. Symbol Tamb t/V
Operating conditions ...continued Parameter ambient temperature input transition rise and VCC = 1.65 V to 2.7 V fall rate VCC = 2.7 V to 5.5 V Conditions Min -40 Max +125 20 10 Unit C ns/V ns/V
10. Static characteristics
Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground 0 V). Symbol Parameter Tamb = -40 C to +85 C[1] VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL LOW-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V VOH HIGH-level output voltage VI = VIH or VIL IO = -100 A; VCC = 1.65 V to 5.5 V IO = -4 mA; VCC = 1.65 V IO = -8 mA; VCC = 2.3 V IO = -12 mA; VCC = 2.7 V IO = -24 mA; VCC = 3.0 V IO = -32 mA; VCC = 4.5 V II IOZ IOFF ICC ICC Ci input leakage current OFF-state output current power-off leakage current supply current additional supply current input capacitance VI = 5.5 V or GND; VCC = 0 V to 5.5 V VI = VIH or VIL; VO = 5.5 V or GND; VCC = 3.6 V VI or VO = 5.5 V; VCC = 0 V VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A per pin; VI = VCC - 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V VCC - 0.1 1.2 1.9 2.2 2.3 3.8 0.1 0.1 0.1 0.1 5 2 5 10 10 10 500 V V V V V V A A A A A pF 0.1 0.45 0.3 0.4 0.55 0.55 V V V V V V 0.65VCC 1.7 2.0 0.7VCC 0.35VCC 0.7 0.8 0.3VCC V V V V V V V V Conditions Min Typ Max Unit
74LVC2G125_10
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 10 -- 11 June 2008
5 of 17
NXP Semiconductors
74LVC2G125
Dual bus buffer/line driver; 3-state
Table 7. Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground 0 V). Symbol Parameter Tamb = -40 C to +125 C VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL LOW-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V VOH HIGH-level output voltage VI = VIH or VIL IO = -100 A; VCC = 1.65 V to 5.5 V IO = -4 mA; VCC = 1.65 V IO = -8 mA; VCC = 2.3 V IO = -12 mA; VCC = 2.7 V IO = -24 mA; VCC = 3.0 V IO = -32 mA; VCC = 4.5 V II IOZ IOFF ICC ICC input leakage current OFF-state output current power-off leakage current supply current additional supply current VI = 5.5 V or GND; VCC = 0 V to 5.5 V VI = VIH or VIL; VO = 5.5 V or GND; VCC = 3.6 V VI or VO = 5.5 V; VCC = 0 V VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A per pin; VI = VCC - 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V VCC - 0.1 0.95 1.7 1.9 2.0 3.4 20 20 20 40 5 V V V V V V A A A A mA 0.1 0.70 0.45 0.60 0.80 0.80 V V V V V V 0.65VCC 1.7 2.0 0.7VCC 0.35VCC 0.7 0.8 0.3VCC V V V V V V V V Conditions Min Typ Max Unit
[1]
Typical values are measured at VCC = 3.3 V and Tamb = 25 C.
74LVC2G125_10
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Product data sheet
Rev. 10 -- 11 June 2008
6 of 17
NXP Semiconductors
74LVC2G125
Dual bus buffer/line driver; 3-state
11. Dynamic characteristics
Table 8. Dynamic characteristics Voltages are referenced to GND (ground 0 V); for test circuit see Figure 9. Symbol Parameter tpd Conditions
[2]
-40 C to +85 C Min Typ[1] 3.7 2.5 2.7 2.3 1.9 4.3 2.8 3.3 2.4 2.0 3.5 1.8 2.7 2.7 1.8 18 5 Max 9.1 4.8 4.8 4.3 3.7 9.9 5.6 5.7 4.7 3.8 11.6 5.8 4.8 4.6 3.4 -
-40 C to +125 C Min 1.0 0.5 1.0 0.5 0.5 1.5 1.0 1.5 0.5 0.5 1.0 0.5 1.0 1.0 0.5 Max 11.4 6.0 6.0 5.5 4.6 12.4 7.0 7.1 5.9 4.8 14.1 7.6 6.2 5.9 4.6 -
Unit
propagation delay nA to nY; see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V
1.0 0.5 1.0 0.5 0.5
[3]
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF
ten
enable time
nOE to nY; see Figure 8 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V
1.5 1.0 1.5 0.5 0.5
[4]
tdis
disable time
nOE to nY; see Figure 8 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V
1.0 0.5 1.0 1.0 0.5
[5]
CPD
power dissipation capacitance
per buffer; VI = GND to VCC output enabled output disabled
-
[1] [2] [3] [4] [5]
Typical values are measured at nominal VCC and at Tamb = 25 C. tpd is the same as tPLH and tPHL. ten is the same as tPZH and tPZL. tdis is the same as tPLZ and tPHZ. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL x VCC2 x fo) = sum of outputs.
74LVC2G125_10
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 10 -- 11 June 2008
7 of 17
NXP Semiconductors
74LVC2G125
Dual bus buffer/line driver; 3-state
12. Waveforms
VI nA input GND
VM
tPHL VOH
nY output VOL
tPLH
VM
mna230
Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7.
Propagation delay input (nA) to output (nY)
VI nOE input GND tPLZ VCC output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled VY VM VM VX tPZH tPZL VM
outputs disabled
outputs enabled
mna362
Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8. Table 9. VCC
3-state output enable and disable times Measurement points Input VM 0.5VCC 0.5VCC 1.5 V 1.5 V 0.5VCC Output VM 0.5VCC 0.5VCC 1.5 V 1.5 V 0.5VCC VX VOL + 0.15 V VOL + 0.15 V VOL + 0.3 V VOL + 0.3 V VOL + 0.3 V VY VOH - 0.15 V VOH - 0.15 V VOH - 0.3 V VOH - 0.3 V VOH - 0.3 V
Supply voltage 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V
74LVC2G125_10
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 10 -- 11 June 2008
8 of 17
NXP Semiconductors
74LVC2G125
Dual bus buffer/line driver; 3-state
VEXT VCC VI VO DUT
RT CL RL RL
G
mna616
Test data is given in Table 10. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. VEXT = Test voltage for switching times.
Fig 9. Table 10. VCC
Load circuitry for switching times Test data Input VI VCC VCC 2.7 V 2.7 V VCC tr, tf 2.0 ns 2.0 ns 2.5 ns 2.5 ns 2.5 ns Load CL 30 pF 30 pF 50 pF 50 pF 50 pF RL 1 k 500 500 500 500 VEXT tPLH, tPHL open open open open open tPZH, tPHZ GND GND GND GND GND tPZL, tPLZ 2VCC 2VCC 6V 6V 2VCC
Supply voltage 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V
74LVC2G125_10
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 10 -- 11 June 2008
9 of 17
NXP Semiconductors
74LVC2G125
Dual bus buffer/line driver; 3-state
13. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2
D
E
A
X
c y HE vMA
Z
8
5
A pin 1 index
A2 A1
(A3)
Lp L
1
e bp
4
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.00 A2 0.95 0.75 A3 0.25 bp 0.38 0.22 c 0.18 0.08 D(1) 3.1 2.9 E(1) 3.1 2.9 e 0.65 HE 4.1 3.9 L 0.5 Lp 0.47 0.33 v 0.2 w 0.13 y 0.1 Z(1) 0.70 0.35 8 0
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC --JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16
Fig 10. Package outline SOT502-2 (TSSOP8)
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Product data sheet
Rev. 10 -- 11 June 2008
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NXP Semiconductors
74LVC2G125
Dual bus buffer/line driver; 3-state
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A X
c y HE vMA
Z
8
5
Q A pin 1 index A2 A1 (A3) Lp L
1
e bp
4
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.15 0.00 A2 0.85 0.60 A3 0.12 bp 0.27 0.17 c 0.23 0.08 D(1) 2.1 1.9 E(2) 2.4 2.2 e 0.5 HE 3.2 3.0 L 0.4 Lp 0.40 0.15 Q 0.21 0.19 v 0.2 w 0.13 y 0.1 Z(1) 0.4 0.1 8 0
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC MO-187 JEITA EUROPEAN PROJECTION
ISSUE DATE 02-06-07
Fig 11. Package outline SOT765-1 (VSSOP8)
74LVC2G125_10 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 10 -- 11 June 2008
11 of 17
NXP Semiconductors
74LVC2G125
Dual bus buffer/line driver; 3-state
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
SOT833-1
1
2
3
b 4 4x L
(2)
L1
e
8 e1
7 e1
6 e1
5
8x
(2)
A
A1 D
E
terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max 0.5 A1 max 0.04 b 0.25 0.17 D 2.0 1.9 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm
Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT833-1 REFERENCES IEC --JEDEC MO-252 JEITA --EUROPEAN PROJECTION ISSUE DATE 07-11-14 07-12-07
Fig 12. Package outline SOT833-1 (XSON8)
74LVC2G125_10 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 10 -- 11 June 2008
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NXP Semiconductors
74LVC2G125
Dual bus buffer/line driver; 3-state
XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 x 2 x 0.5 mm
SOT996-2
D
B
A
E
A
A1
detail X terminal 1 index area e1 L1
1
e
b
4
v w
M M
CAB C
C y1 C y
L2
L
8 5
X
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.35 0.15 D 2.1 1.9 E 3.1 2.9 e 0.5 e1 1.5 L 0.5 0.3 L1 0.15 0.05 L2 0.6 0.4 v 0.1 w 0.05 y 0.05 y1 0.1
OUTLINE VERSION SOT996-2
REFERENCES IEC --JEDEC JEITA ---
EUROPEAN PROJECTION
ISSUE DATE 07-12-18 07-12-21
Fig 13. Package outline SOT996-2 (XSON8U)
74LVC2G125_10 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 10 -- 11 June 2008
13 of 17
NXP Semiconductors
74LVC2G125
Dual bus buffer/line driver; 3-state
XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm
SOT902-1
D terminal 1 index area
B
A
E
A A1
detail X
L1 L
e
4
e v M C A B w M C
5
C y1 C y
3
metal area not for soldering
2 6
b
e1
e1
7 1
terminal 1 index area
8
X
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.25 0.15 D 1.65 1.55 E 1.65 1.55 e 0.55 e1 0.5 L 0.35 0.25 L1 0.15 0.05 v 0.1 w 0.05 y 0.05 y1 0.05
OUTLINE VERSION SOT902-1
REFERENCES IEC --JEDEC MO-255 JEITA ---
EUROPEAN PROJECTION
ISSUE DATE 05-11-25 07-11-14
Fig 14. Package outline SOT902-1 (XQFN8U)
74LVC2G125_10 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 10 -- 11 June 2008
14 of 17
NXP Semiconductors
74LVC2G125
Dual bus buffer/line driver; 3-state
14. Abbreviations
Table 11. Acronym CMOS DUT ESD HBM MM TTL Abbreviations Description Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic
15. Revision history
Table 12. Revision history Release date 20080611 Data sheet status Product data sheet Change notice Supersedes 74LVC2G125_9 Document ID 74LVC2G125_10 Modifications:
* *
Section 8: derating factor for TSSOP8, VSSOP8, XSON8, XSON8U and XQFN8U package added Added type number 74LVC2G125GD (XSON8U package) Product data sheet Product data sheet Product data sheet Product data sheet Product specification Product specification Product specification Product specification Product specification 74LVC2G125_8 74LVC2G125_7 74LVC2G125_6 74LVC2G125_5 74LVC2G125_4 74LVC2G125_3 74LVC2G125_2 74LVC2G125_1 -
74LVC2G125_9 74LVC2G125_8 74LVC2G125_7 74LVC2G125_6 74LVC2G125_5 74LVC2G125_4 74LVC2G125_3 74LVC2G125_2 74LVC2G125_1
20080226 20070907 20060523 20051223 20050201 20040922 20040109 20030901 20030310
74LVC2G125_10
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 10 -- 11 June 2008
15 of 17
NXP Semiconductors
74LVC2G125
Dual bus buffer/line driver; 3-state
16. Legal information
16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
16.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVC2G125_10
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 10 -- 11 June 2008
16 of 17
NXP Semiconductors
74LVC2G125
Dual bus buffer/line driver; 3-state
18. Contents
1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 11 June 2008 Document identifier: 74LVC2G125_10

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